In one conventional data processing system, data packets travel through the system through many buses, memory buffers, DMA control blocks, etc., between the origin and the final destination. Some conventional systems employ a design that has data flowing through the system in a small packet data format. In order to minimize I/O (input/output) processing latency, many conventional systems employ a pipelined data processing design, i.e., before the last data packet reaches a destination, the source issues a request (transfer) of the next data packet. In order to sustain the integrity of data, some conventional systems must be able to keep track of all outstanding data packets until each of the packets reach their destination. Moreover, in conventional data processing systems, if an error occurs while the data packet is traveling through the system, I/O control mechanisms must be able to correlate the error reported from an I/O with an outstanding data packet from the I/O. This type of control tends to be particularly complex, especially when handled by a single I/O control mechanism. Moreover, in some conventional system, when an error gets reported the system may halt data transfers on that I/O until the error is sorted out, or alternatively, an interrupt is generated to halt all data flow along a particular data path. Thus, conventional data processing systems are incapable of handling errors without requiring significant processor interaction and further, without suspending operations along a data path.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.